Well one may ask, why not just use open collector for shared bus systems. Which means the output of the logic is floating. In later, when a logic is not driving it output, it does not drive LOW and also does not drive HIGH.
Normally when we have to implement shared bus system inside a ASIC or external to the chip, we have two options, either to use MUX/DEMUX based system or, use tri-state base bus system. Thus shorting the negative voltage to ground. Q4 is in cut-off).ĭiodes in input are protection diodes, which conduct when there is large negative voltage at input. Q3 is called pull-up transistor, as it pulls the output voltage up, when it saturates and other is in cut-off (i.e. Q4 is called pull-down transistor, as it pulls the output voltage down, when it saturates and other is in cut-off (i.e. Q2 provides complementary voltages for the output transistors Q3 and Q4, which stacked one above the other in such a way that while one of these conducts, the other is cut-off. Output stage is called Totem-Pole because, the transistor Q3 sites upon Q4. Input stage and Phase splitter stage has already been discussed. This in turn drives the phase splitter transistor into cut-off.īelow is the circuit of a totem-pole NAND gate, which has got three stages. emitter base junction is forward biased and input transistor conducts. When any of the input is driven low, i.e. Input stage consists of multi emitter transistor as shown in figure below. This consists of input transistor and phase splitter transistor. As such all the families of TTL have three configuration for outputs.īefore we discuss the output stage lets looks at the input stage, which is used almost with all the versions of TTL. Here we will discuss only basic TTL as of now, may be in future, I will add more details about other versions of TTL. There are many versions or families of TTL Through the years basic TTL has been improved to meet the performance requirements. Transistor Transistor logic or just TTL, logic gates are built around only transistors.
TOTEM POLE OUTPUT STAGE SERIES
If all the inputs X, Y, Z are driven high, the series diodes conduct and thus driving transistor into saturation. Hence the transistor does not conduct, thus remains in cut-off, and output out is High. Thus there is no current through the diodes connected in series to transistor base. If input X, Y, Z is low, the corresponding diode conducts current, thorough the 4.7K resistor. The diodes and the 4.7K resistor form an AND gate. Each of the input is associated with one diode. Basic circuit in the DTL logic family is as shown in figure below. In DTL (Diode transistor logic), all the logic are implemented using diodes, and transistors.
When either of input X or Y is driven HIGH, corresponding transistor is goes to saturation and output Z is pulled to LOW. Below is the example of few RTL logic circuits.Ī basic circuit of an RTL NOR gate consists of two transistors Q1 and Q2, connected as shown in figure above.
One basic thing about the transistor (NPN), is that HIGH at input causes output to be LOW (i.e. In RTL (resistor transistor logic), all the logic are implemented using resistors and transistors. Diode Logic is used extensively but not in integrated circuits.Diode Logic only permits the OR and AND functions.Diode Logic suffers from voltage degradation from one stage to the next.When anyone one the diode conduct, out Z goes high. When high is applied to either X or Y, or Both X and Y are driven high, corresponding diode get forward biased and thus making diodes to conduct. When there is no input is connected or driven, output Z is low, due resistor R1. Below is the example of few RTL logic circuits. One basic thing about the diode, is that diode needs to be forward biased to make it conduct. In DL (diode logic), all the logic are implemented using diodes and resistors.
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